publication venue for
- Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. 64:48-53. 2016
- Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology. 55:1323-1327. 2015
- Compact thermal modeling of spin transfer torque magnetic tunnel junction. 55:1649-1653. 2015
- A dual-rail compact defect-tolerant multiplexer. 55:662-670. 2015
- Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. 55:696-703. 2015
- Cross-layer investigation of continuous-time sigma–delta modulator under aging effects. 55:645-653. 2014
- A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. 53:1189-1193. 2013
- Progressive module redundancy for fault-tolerant designs in nanoelectronics. 51:1489-1492. 2011
- Fast reliability analysis of combinatorial logic circuits using conditional probabilities. 50:1215-1218. 2010
- Using error tolerance of target application for efficient reliability improvement of digital circuits. 50:1219-1222. 2010
- An efficient tool for reliability improvement based on TMR. 50:1247-1250. 2010