selected publications
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academic article
- Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping. EURASIP Journal on Embedded Systems. 2017. 2017
- Complexity adaptive iterative receiver performing TBICM-ID-SSD. EURASIP Journal on Advances in Signal Processing. 2012. 2012
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chapter
- ASIP Design for Multi-Standard Channel Decoders. Springer eBooks. 151-175. 2014
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conference paper
- Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN. 2022 IEEE International Symposium on Circuits and Systems (ISCAS). 1-5. 2020
- Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. . 87-93. 2013
- Parameterized Area-efficient Multi-standard Turbo Decoder. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015. 109-114. 2013
- An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. . 1-6. 2012
- Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm<sup>2</sup> multi-standard turbo decoder. . 1-7. 2012
- FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. . 143-148. 2012
- Adaptive complexity MIMO turbo receiver applying turbo demodulation. . 235-239. 2012
- Complexity reduction of shuffled parallel iterative demodulation with turbo decoding. . 1-6. 2012
- Area and throughput optimized ASIP for multi-standard turbo decoding. . 79-84. 2011
- Exploring parallel processing levels in turbo demodulation. . 359-363. 2010
- Rapid design and prototyping of universal soft demapper. . 3769-3772. 2010
- Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. . 130-133. 2009
- ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. . 1620-1625. 2009
- Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. . 429-434. 2008
- On-chip communication network for flexible multiprocessor turbo decoding. . 1-6. 2008
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